Method for fabricating semiconductor device

ABSTRACT

A semiconductor device includes a device isolation structure formed on a semiconductor substrate to define an active region. A first Si-based epitaxial pattern is formed over the active region corresponding to a bit line contact region and a portion of a gate region at both sides adjacent to the bit line contact region. A second Si-based epitaxial layer is formed over the semiconductor substrate which is stepped up on the first Si-based epitaxial pattern. A stepped gate pattern is formed over the stepped second Si-based epitaxial layer.

CROSS-REFERENCES TO RELATED APPLICATIONS

The present invention is a divisional of U.S. patent application Ser.No. 11/822,650, filed on Jul. 9, 2007, which is a continuation-in-partof U.S. patent application Ser. No. 11/169,707, filed on Jun. 30, 2005,and claims priority of Korean patent application number 10-2005-0024932,filed on Mar. 25, 2005, which are incorporated by reference in theirentirety.

BACKGROUND OF THE INVENTION

1. Field of the Invention

The present invention generally relates to a method for fabricating asemiconductor device, and more specifically to a method for fabricatinga semiconductor device wherein a gate is formed on a stepped Siepitaxial layer to increase an effective length of a gate channel, andan oxide film is only formed at the interface of the Si epitaxial layerand the semiconductor substrate where a bit line contact is to beformed, thereby improving a characteristic of a leakage current for astorage node junction.

2. Description of the Related Art

FIG. 1 is a layout illustrating a method for fabricating a semiconductordevice, wherein reference numerals 1000 a, 1, 2 and 3 denote a cellregion, an active region, a first gate region and a second gate region,respectively. The first gate region 2 is overlapped the second gateregion 3. A line width of the first gate region 2 is less than a widthof the second gate region 3.

FIGS. 2 a through 2 f are cross-sectional views illustrating a methodfor fabricating a semiconductor device, wherein FIGS. 2 a(i) through 2f(i) are cross-sectional views taken along the line I-I′ in FIG. 1, andFIGS. 2 a(ii) through 2 f(ii) are cross-sectional views in acore/peripheral circuit region 1000 b.

Referring to FIG. 2 a, a stacked structure of a SiGe epitaxial layer(not shown), a first Si epitaxial layer (not shown), a first oxide film(not shown) and a first nitride film (not shown) is formed on asemiconductor substrate 10 having a cell region 1000 a and acore/peripheral circuit region 1000 b defined therein. Next, a firstphotoresist film (not shown) is deposited on the entire surface of thefirst nitride film (not shown) in the cell region 1000 a and thecore/peripheral circuit region 1000 b. Thereafter, the first photoresistfilm (not shown) is exposed and developed to form a first photoresistfilm pattern (not shown) exposing the first gate region 2 of FIG. 1 andcovering the entire core/peripheral circuit region 1000 b. After that,the stacked structure is etched using the first photoresist film patternas an etching mask to expose the semiconductor substrate 10corresponding to the first gate region 2 and the entire core/peripheralcircuit region 1000 b. The first photoresist film pattern is thenremoved.

Referring FIG. 2 b, a first nitride film pattern 19 and a first oxidefilm pattern 17 in the cell region 1000 a are removed via a wet etchingmethod. Next, a second Si expitaxial layer 25 is formed on the entiresurface of the cell region 1000 a and the core/peripheral circuit region1000 b.

Referring to FIG. 2 c, a second oxide film 30 and a second nitride film35 are formed on the second Si epitaxial layer 25 in the cell region1000 a and the core/peripheral circuit region 1000 b. Next, a secondphotoresist film (not shown) is deposited on the entire surface of thesecond nitride film 35. The second photoresist film is then exposed anddeveloped to form a second photoresist film pattern (not shown) definingthe active region 1 of FIG. 1 in the cell region 1000 a, and also anactive region in the core/peripheral circuit region 1000 b. Thereafter,the second nitride film 35, the second oxide film 30, the second Siepitaxial layer 25, the first Si epitaxial layer pattern 15, the SiGeepitaxial layer pattern 13 and a given thickness of the semiconductorsubstrate 10 are etched using the second photoresist film pattern as anetching mask to form a trench 40 in the cell region 1000 a and thecore/peripheral circuit region 1000 b. After that, the secondphotoresist film pattern (not shown) is removed. The SiGe epitaxiallayer pattern 13 is then etched through a sidewall of the trench 40 viaa wet etching method to form a space 27 under the first Si epitaxiallayer pattern 15.

Referring to FIG. 2 d, a gap-filling insulating film 45 is formed on theentire surface to fill up the space 27 and the trench 40 in the cellregion 1000 a and to fill up the trench 40 in the core/peripheralcircuit region 1000 b. Next, the gap-filling insulating film 45 ispolished until the second nitride film 35 is exposed. The gap-fillinginsulating film 45 serves as a device isolation structure. Thereafter, agiven thickness of the gap-filling insulating film 45 in the trench 40is etched. The second nitride film 35 is then removed via a wet etchingmethod. After that, a well implant process and a channel implant processare performed so as to adjust impurity concentrations in the cell region1000 a and the core/peripheral circuit region 1000 b.

Referring to FIG. 2 e, the second oxide film 30 in the cell region 1000a and the core/peripheral circuit region 1000 b is removed via a wetetching method to expose the second Si epitaxial layer 25. A gate oxidefilm 50 is then formed on the exposed second Si epitaxial layer 25.Next, gate conductive layers 60 and 70, and a hard mask insulating film80 are formed on the gate oxide film 50 and the gap-filling insulatingfilm 45 in the cell region 1000 a and the core/peripheral circuit region1000 b.

Referring to FIG. 2 f, a third photoresist film (not shown) is depositedon the hard mask insulating film 80 in the cell region 1000 a and thecore/peripheral circuit region 1000 b. Thereafter, the third photoresistfilm (not shown) is exposed and developed to form a third photoresistfilm pattern defining the second gate region 3 of FIG. 1 and a gateregion (not shown) in the core/peripheral circuit region 1000 b.Specifically, the third photoresist film pattern exposes a bit linecontact region and storage node contact regions in the cell region 1000a and covers a region where a gate is to be formed in thecore/peripheral circuit region 1000 b. Next, the hard mask insulatingfilm 80 and the gate conductive layers 70 and 60 are etched using thethird photoresist film pattern as an etching mask to respectively form agate 90 in the cell region 1000 a and the core/peripheral circuit region1000 b.

However, in accordance with the above-described method, the gate 90 isformed on a plane second Si epitaxial layer. As a result, a gate channellength is decreased as a design rule of the semiconductor device isreduced. Moreover, an oxide film is formed at the interface of the Siepitaxial layer and the semiconductor substrate where a storage nodecontact is to be formed. Accordingly, the leakage current for a storagenode junction is highly depended upon an interface characteristicbetween the Si epitaxial layer and an oxide film. In addition, the SiGeepitaxial layer under the storage node contact is removed for forming adevice isolation film. As a result, Ge in the SiGe epitaxial layer isdiffused into the first Si epitaxial layer, the second Si epitaxiallayer and the semiconductor substrate due to heat treatment processesprior to the formation of the device isolation film. Accordingly, theleakage current for the storage node junction is increased.

SUMMARY OF THE INVENTION

Embodiments of the invention are directed to a semiconductor deviceincluding a stepped gate. According to one embodiment of the invention,a stepped gate is formed over a stepped structure that is formed of astacked structure of a Si epitaxial layer and an insulating film. As aresult, a length of the gate channel is increased.

According to one embodiment of the invention, a semiconductor deviceincludes: a device isolation structure formed on a semiconductorsubstrate to define an active region; a first Si-based epitaxial patternformed over the active region corresponding to a bit line contact regionand a portion of a gate region at both sides adjacent to the bit linecontact region; a second Si-based epitaxial layer formed over thesemiconductor substrate which is stepped up on the first Si-basedepitaxial pattern; and a stepped gate pattern formed over the steppedsecond Si-based epitaxial layer.

According to another embodiment of the invention, a semiconductor deviceincludes: a device isolation structure formed on a semiconductorsubstrate to define an active region; a first Si-based epitaxial patternformed over the active region corresponding to a bit line contact regionand a portion of a gate region at both sides adjacent to the bit linecontact region; a second Si-based epitaxial layer formed over thesemiconductor substrate; and a gate formed over the second Si-basedepitaxial layer, wherein the semiconductor device is characterized inthat the second Si-based epitaxial layer is formed to be stepped up onthe first Si-based epitaxial pattern.

According to one embodiment of the invention, a method of fabricating asemiconductor device includes: forming a first Si-based epitaxialpattern over a semiconductor substrate corresponding to a bit linecontact region and a portion of gate regions adjacent to the bit linecontact region; forming a second Si-based epitaxial layer over thesemiconductor substrate, wherein the second Si-based epitaxial layer isstepped up on the first Si-based epitaxial pattern; etching the secondSi-based epitaxial layer, the first Si-based epitaxial pattern, and aportion of the semiconductor substrate by using a device isolation maskto form a trench defining an active region; removing a portion of thefirst Si-based epitaxial pattern through a sidewall of the trench toform an under-cut space; forming a device isolation structure to fillthe under-cut space and the trench; forming a gate insulating film overthe stepped second Si-based epitaxial layer; and forming a stepped gatepattern over the semiconductor substrate including the stepped secondSi-based epitaxial layer.

According to another embodiment of the invention, a method offabricating a semiconductor device includes: forming a first Si-basedepitaxial pattern over a semiconductor substrate corresponding to a bitline contact region and a portion of gate regions adjacent to the bitline contact region; forming a second Si-based epitaxial layer over thesemiconductor substrate; etching the second Si-based epitaxial layer,the first Si-based epitaxial pattern, and a portion of the semiconductorsubstrate by using a device isolation mask to form a trench defining anactive region; removing a portion of the first Si-based epitaxialpattern through a sidewall of the trench to form an under-cut space;forming a device isolation structure to fill the under-cut space and thetrench; forming a gate insulating film over the stepped second Si-basedepitaxial layer; and forming a stepped gate pattern over thesemiconductor substrate including the stepped second Si-based epitaxiallayer, wherein the method is characterized in that the second Si-basedepitaxial layer is stepped up on the first Si-based epitaxial pattern.

BRIEF DESCRIPTION OF THE DRAWINGS

FIG. 1 is a layout illustrating a method for fabricating a semiconductordevice.

FIGS. 2 a through 2 f are cross-sectional views illustrating a methodfor fabricating a semiconductor device.

FIG. 3 is a layout illustrating a method for fabricating a semiconductordevice in accordance with an embodiment of the present invention.

FIGS. 4 a through 4 f and FIG. 5 are cross-sectional views illustratinga method for fabricating a semiconductor device according to anembodiment of the present invention.

DETAILED DESCRIPTION OF THE EXEMPLARY EMBODIMENTS

Reference will now be made in detail to exemplary embodiments of thepresent invention. Wherever possible, the same reference numbers will beused throughout the drawings to refer to the same or like parts.

FIG. 3 is a layout illustrating a method for fabricating a semiconductordevice in accordance with an embodiment of the present invention,wherein reference numerals 2000 a, 101, 103, 105, and 107 denote a cellregion, an active region, a gate region, a step region, and a bit linecontact region, respectively. The step region 105 includes a bit linecontact region 107 and a portion of a gate region 103 at both sidesadjacent to the bit line contact region 107. A line width of the stepregion 105 is N, where F<N≦7/3F, and F is a distance between twoneighboring gate regions 103.

FIGS. 4 a through 4 f illustrate a method for fabricating asemiconductor device according to an embodiment of the presentinvention, wherein FIGS. 4 a(i) through 4 f(i) are cross-sectional viewstaken along the line II-II′ of FIG. 3, and FIGS. 4 a(ii) through 4 f(ii)are cross-sectional views in a core/peripheral circuit region 2000 b.

Referring to FIG. 4 a, a stacked structure of a SiGe epitaxial layer(not shown), a first Si-based epitaxial layer (not shown) and aninsulating film (not shown) is formed over a semiconductor substrate 110having a cell region 2000 a and a core/peripheral circuit region 2000 bdefined therein. Preferably, the insulating film comprises an oxide filmor a stacked structure of an oxide film and a nitride film. Next, afirst photoresist film (not shown) is deposited over the entire surfaceof the insulating film in the cell region 2000 a and the core/peripheralcircuit region 2000 b. Thereafter, the first photoresist film (notshown) is exposed and developed to form a first photoresist pattern 121covering the step region 105 of FIG. 3 and exposing the entirecore/peripheral circuit region 2000 b. The step region 105 includes abit line contact region 107 and a portion of the gate region 103 at bothsides adjacent to the bit line contact region 107. Preferably, a linewidth of the step region 105 is N, where F<N≦7/3F, and F is a distancebetween two neighboring gate regions 103. After that, the stackedstructure is etched using the first photoresist pattern 121 as anetching mask to expose the semiconductor substrate 110 where a storagenode contact region and a portion of the gate region 103 at both sidesadjacent to the storage node contact region and the entirecore/peripheral circuit region 2000 b. An insulating film pattern 120, afirst Si-based epitaxial pattern 115, and a SiGe epitaxial pattern 113are formed over the step region. The first photoresist film pattern 121is then removed. In one embodiment of the present invention, theSi-based epitaxial layer is formed with Si. In addition, the Si-basedepitaxial layer may be formed with Si and additions such as Ge.

Referring to FIG. 4 b, the insulating film pattern 120 in the cellregion 2000 a is removed. Preferably, the process of removing theinsulating film pattern 120 is performed by a wet etching method. Next,a stepped second Si epitaxial layer 125 is formed over the semiconductorsubstrate in the cell region 2000 a and the core/peripheral circuitregion 2000 b. Preferably, a thickness of the second Si-based epitaxiallayer 125 is in a range of about 10˜100 nm. The second Si-basedepitaxial layer 125 in the cell region 2000 a has a step differencesince the second Si-based epitaxial layer 125 in the cell region 2000 ais stepped up on a stacked structure of the first Si-based epitaxialpattern 115 and the SiGe epitaxial pattern 113.

Referring to FIG. 4 c, a second oxide film 130 and a second nitride film135 are formed over the stepped second Si-based epitaxial layer 125 inthe cell region 2000 a and the core/peripheral circuit region 2000 b.Next, a second photoresist film (not shown) is deposited over the entiresurface of the second nitride film 135. The photoresist film is thenexposed and developed to form a second photoresist pattern (not shown)to define the active region 101 of FIG. 3 in the cell region 2000 a andalso an active region in the core/peripheral circuit region 2000 b.Thereafter, the second nitride film 135, the second oxide film 130, thesecond Si-based epitaxial layer 125, the first Si-based epitaxialpattern 115, the SiGe epitaxial pattern 113 and a portion of thesemiconductor substrate 110 are etched using the second photoresistpattern as an etching mask to form a trench 140 in the cell region 2000a and the core/peripheral circuit region 2000 b. After that, the secondphotoresist pattern is removed. The SiGe epitaxial pattern 113 is thenetched through a sidewall of the trench 140 to form an under-cut space127 under the first Si-based epitaxial layer pattern 115.

FIG. 5 is a cross-sectional view taken along the line III-III′ of FIG. 3illustrating the structure of FIG. 4 c(i) including the space 127 havingan under-cut structure.

Preferably, the process of removing the SiGe epitaxial pattern 113 ispreformed by a wet etching method, a plasma etching method, and acombination thereof. The wet etching method utilizes a mixed etchantcontaining HF, H₂O₂ and CH₃CHOOH. The plasma etching method utilizes amixed gas containing (CF₃ or CH₂F₂), N₂ and O₂, and combinationsthereof. Moreover, a volume ratio of HF, H₂O₂ and CH₃COOH in the mixedetchant is preferably about 1:2:3.

Referring to FIG. 4 d, a gap-filling insulating film 145 is formed overthe entire surface to at least fill up the under-cut space 127 and thetrench 140 in the cell region 2000 a and to fill up the trench 140 inthe core/peripheral circuit region 2000 b. Preferably, the process offorming the gap-filling insulating film 145 may include forming athermal oxide film to fill the under-cut space 127 and forming an oxidefilm for device isolation to fill the trench 140. A nitride film may befurther formed at an interface of the thermal oxide film and the oxidefilm for device isolation. Moreover, the process of forming thegap-filling insulating film 145 may include forming a thermal oxide filmto fill up a portion of the under-cut space 127, forming a nitride filmto fill up the remaining portion of the under-cut space 127, and formingan oxide film for device isolation to fill up the trench 140. Next, thegap-filling insulating film 145 is polished until the second nitridefilm 135 is exposed. The gap-filling insulating film 145 in the trench140 serves as a device isolation structure. Thereafter, a portion of thegap-filling insulating film 145 in the trench 140 is etched. The secondnitride film 135 is then removed. Preferably, the process of etching thegap-fill insulating film 145 is performed by a wet etching method. Theprocess of removing the second nitride film 135 is preferably preformedby a wet etching method. After that, well implant and channel implantprocesses are performed so as to respectively adjust impurityconcentrations in the cell region 2000 a and the core/peripheral circuitregion 2000 b.

Referring to FIG. 4 e, the second oxide film 130 in the cell region 2000a and the core/peripheral circuit region 2000 b is removed to expose thestepped second Si-based epitaxial layer 125. A gate oxide film 150 isthen formed over the stepped second Si-based epitaxial layer 125.Preferably, the process of etching the second oxide film 130 isperformed by a wet etching method. Next, a stacked structure of a gateconductive layer 175 and a gate hard mask layer 180 is formed over thegate oxide film 150 and the gap-filling insulating film 145 in the cellregion 2000 a and the core/peripheral circuit region 2000 b. Preferably,the gate conductive layer 175 comprises a lower conductive layer 160 andan upper conductive layer 170.

Referring to FIG. 4 f, a third photoresist film (not shown) is depositedover the gate hard mask layer 180 in the cell region 2000 a and thecore/peripheral circuit region 2000 b. Thereafter, the third photoresistfilm (not shown) is exposed and developed to form a third photoresistpattern to define the gate region 103 of FIG. 3 and a gate region in thecore/peripheral circuit region 2000 b. Specifically, the thirdphotoresist pattern exposes a bit line contact region 107 and storagenode contact regions in the cell region 2000 a and covers a region wherea gate is to be formed in the core/peripheral circuit region 2000 b.Next, the stacked structure is patterned using the third photoresistpattern as an etching mask to respectively form a stepped gate 190 inthe cell region 2000 a and a gate in the core/peripheral circuit region2000 b. Thus, the gap-filling insulating film 145 is disposed only inthe bit line contact region 107 of FIG. 3 and a portion under thestepped gate 190 adjacent to the bit line contact region 107. Inaddition, subsequent processes such as an ion-implant process forforming source/drain regions in the active regions, a process forforming a spacer on a sidewall of the gate 190, a process for forming alanding plug, a process for forming a bit line contact and a bit line, aprocess for forming a capacitor and a process for forming aninterconnect may be done.

As described above, the method for fabricating a semiconductor device inaccordance with the present invention provides exposing the contactregion including the storage node contact region and a portion of thegate region adjacent thereto and only forming an oxide film at theinterface of the Si epitaxial layer under both a bit line contact regionand a portion of a gate region at both sides adjacent to the bit linecontact region and the underlying semiconductor substrate. Accordingly,capacitance for a bit line contact and a short-channel effect of a celltransistor are improved.

As shown in FIG. 4 f, the gate 190 in the cell region 2000 a is formedover a stepped structure instead of over a plane structure to increasean effective length of the gate channel. The storage node contact isformed over the Si epitaxial layer without the oxide film to minimizethe leakage current of the storage node junction. Accordingly, a refreshcharacteristic of a DRAM can be improved.

The foregoing description of various embodiments of the invention hasbeen presented for purposes of illustration and description. It is notintended to be exhaustive or to limit the invention to the precise formdisclosed, and modifications and variations are possible in light of theabove teachings or may be acquired from practice of the invention. Theembodiments were chosen and described in order to explain the principlesof the invention and its practical application to enable one skilled inthe art to utilize the invention in various embodiments and with variousmodifications as are suited to the particular use contemplated.

1.-3. (canceled)
 4. A method for fabricating a semiconductor device, themethod comprising: forming a first Si-based epitaxial pattern over asemiconductor substrate corresponding to a bit line contact region and aportion of gate regions adjacent to the bit line contact region; forminga second Si-based epitaxial layer over the semiconductor substrate,wherein the second Si-based epitaxial layer is stepped up on the firstSi-based epitaxial pattern; etching the second Si-based epitaxial layer,the first Si-based epitaxial pattern, and a portion of the semiconductorsubstrate by using a device isolation mask to form a trench defining anactive region; removing a portion of the first Si-based epitaxialpattern through a sidewall of the trench to form an undercut space;forming a device isolation structure to fill the under-cut space and thetrench; forming a gate insulating film over the stepped second Si-basedepitaxial layer; and forming a stepped gate pattern over thesemiconductor substrate including the stepped second Si-based epitaxiallayer.
 5. The method according to claim 4, wherein the process offorming a first Si-based epitaxial pattern comprises: forming a SiGeepitaxial layer and a first Si-based epitaxial layer over asemiconductor substrate; forming a photoresist film over thesemiconductor substrate; exposing and developing the photoresist film toform a photoresist pattern covering the first Si-based epitaxial layercorresponding to the bit line contact region and a portion of a gateregion at both sides adjacent to the bit line contact region; andetching the Si-based epitaxial layer and the SiGe epitaxial layer byusing the photoresist pattern as an etching mask.
 6. The methodaccording to claim 5, wherein the line width of the photoresist patternis N, where F<N≦7/3F and F is a distance between two neighboring gateregions).
 7. The method according to claim 4, wherein a thickness of thesecond Si-based epitaxial layer is in a range of about 10˜100 nm.
 8. Themethod according to claim 4, wherein the process of removing a portionof the first Si-based epitaxial pattern is performed through one methodselected from the group consisting of a wet etching method, a plasmaetching method and a combination thereof, wherein the wet etching methodutilizes a mixed etchant containing HF, H₂O₂ and CH₃COOH, and the plasmaetching method utilizes a mixed gas containing (CF₄ or CH₂F₂), N₂ andO₂.
 9. The method according to claim B, wherein a volume ratio of HF,H₂O₂ and CH₃COOH in the mixed etchant is about 1:2:3.
 10. The methodaccording to claim 4, wherein the process of forming a device isolationstructure comprises: forming a thermal oxide film to fill the under-cutspace; and forming an oxide film for a device isolation to fill thetrench.
 11. The method according to claim 10, further comprising forminga nitride film at the interface of the thermal oxide film and the oxidefilm for the device isolation.
 12. The method according to claim 4,wherein the process of forming a device isolation structure comprises:forming a thermal oxide film to fill a portion of the under-cut space;forming a nitride film to fill a remaining portion of the under-cutspace; and forming an oxide film for the device isolation to fill thetrench. 13.-14. (canceled)
 15. A method for fabricating a semiconductordevice, the method comprising: forming a first Si-based epitaxialpattern over a semiconductor substrate corresponding to a bit linecontact region and a portion of gate regions adjacent to the bit linecontact region; forming a second Si-based epitaxial layer over thesemiconductor substrate; etching the second Si-based epitaxial layer,the first Si-based epitaxial pattern, and a portion of the semiconductorsubstrate by using a device isolation mask to form a trench defining anactive region; removing a portion of the first Si-based epitaxialpattern through a sidewall of the trench to form an undercut space;forming a device isolation structure to fill the under-cut space and thetrench; forming a gate insulating film over the stepped second Si-basedepitaxial layer; and forming a stepped gate pattern over thesemiconductor substrate including the stepped second Si-based epitaxiallayer, wherein the method is characterized in that the second Si-basedepitaxial layer is stepped up on the first Si-based epitaxial pattern.